How a UART makes its baud rate
A UART derives its bit timing from a peripheral clock. It divides the clock by an integer and samples each bit several times, usually 16× (some chips offer 8× for higher speeds):
Divisor = round(f_clock ÷ (oversampling × baud)) Actual baud = f_clock ÷ (oversampling × divisor) Error = actual ÷ target − 1
Because the divisor must be a whole number, most clock and baud combinations leave a small error.
Example: the classic Arduino case
A 16 MHz ATmega at 115,200 baud with 16× sampling needs a divisor of 8.68. Rounded to 9, the UART actually runs at 111,111 baud, an error of −3.5%. Many links still work, but they are fragile. Switching to 8× sampling (the U2X bit) gives a divisor of 17, 117,647 baud and +2.1%, which is much safer. On AVR chips, the UBRR register holds divisor − 1.
How much error is acceptable
A receiver resynchronizes on each start bit and must still sample the last stop bit within its window. With 10-bit frames:
| Total mismatch | Result |
|---|---|
| Under ±2% | Reliable |
| 2 to 4% | Works only if the other side is accurate |
| Over 4 to 5% | Corrupted frames |
The limit applies to the sum of both ends’ errors, so two devices at −2.5% and +2.5% will fail.
Baud-friendly crystals
Frequencies such as 1.8432, 3.6864, 7.3728, 11.0592, 14.7456 and 18.432 MHz divide exactly into all standard rates and give 0% error. Modern chips with fractional baud generators (STM32, ESP32, many ARM parts) reduce the problem, but the arithmetic is the same.
Throughput
Each byte is sent as a frame: 1 start bit, 7 to 9 data bits, an optional parity bit and 1 or 2 stop bits. With 8N1 (8 data, no parity, 1 stop), a frame is 10 bits, so 115,200 baud carries at most 11,520 bytes per second, and each byte takes about 87 µs.